The present invention relates, in general, to the field of integrated circuit devices. More particularly, the present invention relates to a configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM.
Delay Locked Loops (DLLs) are used in semiconductor memory devices to align the output data with the system clock. In conventional DLL designs for memory devices, a phase detector is utilized to compare the rising edges of a buffered system clock with a feedback signal in order to adjust the delay of a variable delay line until the rising edges of the two signals are aligned. In operation, if a replica delay in the feedback path of the DLL exactly matches the sum of the input buffer and output data path delays, the output data will then be aligned with the input clock since the delay between them must be a multiple of the clock period when the DLL is locked.
In general, the variable delay lines used in DLLs fall into two broad categories. The first category is defined as a voltage controlled, or “analog”, delay line and is implemented with a fixed number of individual delay elements whose delay is changed by varying a control voltage. Herein, voltage-controlled delay elements or delay lines will be referred to as analog delay elements or analog delay lines and the term analog control will mean voltage-controlled delay. The second category is defined as a digital delay line and utilizes a variable number of individual delay elements whose delay is fixed (e.g. for a given manufacturing process corner, supply voltage and temperature) and the number of delay elements is digitally varied. Herein, fixed delay elements or delay lines will be referred to as fixed or digital delay elements or digital delay lines.
In some designs, a combination of both categories of delay lines have been combined because adjusting the delay of a digital delay line tends to be faster, while the resolution of an analog delay line is finer. An example of an existing DLL design that employs a combination analog/digital delay locked loop is described in U.S. Pat. No. 6,628,154 issued on Sep. 30, 2003. In the design described, the DLL initially locks by digitally selecting the number of delay elements (or stages) in the delay chain and subsequently uses voltage control to fine tune the delay of the elements. However, the design of this particular DLL implementation employs a traditional closed loop architecture for selecting the number of delay stages and for adjusting the analog control voltage to adjust the delay per stage.
During the initial locking of the DLL, the phase comparison is made on each cycle and the number of delay stages is increased or decreased by a single stage until a “course” lock condition is achieved. Subsequently, the delay of each stage is fine-tuned using voltage control. The maximum number of stages in the delay line is determined by the lowest frequency for which the DLL must lock since, in the worst case, a full clock period of adjustment range is required. Since the digital locking is implemented in a closed loop architecture, with a comparison and a single stage adjustment being made on each clock cycle, the digital locking time can require a significant number of clock cycles. Further, since there can be a significant delay between when an adjustment is made and when the phase detector recognizes the change, due to the delay through the delay line, it is also possible to have an unstable locking condition.